![]() The size and complexity of a design is no excuse for missing a CDC bug. Flat SoC verification covers all the critical issues briefly described above: Metastability, glitches and loss of coherency in addition to functional requirements of the asynchronous interfaces and other critical issues across data, control, clock and reset circuitry. In flat SoC verification, the entire SoC is verified in a single run. Approaching CDC analysis of this system requires a systematic methodology. All of this is very manageable at the IP level but can quickly become overwhelming at the SoC level without a disciplined methodology.įor a typical SoC (as shown below) you often have multiple peripheral interfaces, high performance internal compute engines, accelerators and bus fabric, hence multiple clock domains, also multiple power domains and, quite probably, dynamic voltage and frequency selection in several of these domains. Little work has been attempted to tackle clock domain crossing (CDC) verification signoff of large system-on-chip (SoC) designs.ĬDC analysis at the IP level requires some care – there are multiple factors related to which clocks are truly asynchronous, which clocks can be simultaneously active, which crossings are allowed to operate without standard synchronizers (for example, configuration signals which are known to be static through most of the operation of the system) and more. While the concepts and methodologies for verification of such issues have been extensively researched in the past ten years, practical solutions have been offered primarily at the IP-level. ![]() ![]() Data coherency issues occur in a design when multiple synchronizers settle to their new values in different cycles and subsequently interact in downstream logic. Glitches on asynchronous boundaries can also cause defects, since a glitch on an asynchronous crossing can trigger the capture of an incorrect signal transition. FIFOs, 2-phase and 4-phase handshakes are typical structures used for this type of synchronization. While metastability cannot be eliminated, it is usually tolerated by adding a multi-flop synchronizer to control asynchronous boundaries and using those synchronizers to block the destination of an asynchronous boundary when its source is changing. A flip-flop has metastability issues if the clock and data change very closely in time, causing the output to be at an unknown logic value for an unbounded period of time. Metastability is one of the major defects. Incorrect asynchronous boundaries can lead to multiple design defects not encountered in simpler designs. This demands that design and verification teams spend an increasing amount of time verifying the correctness of asynchronous boundaries in the design. As design sizes continue to grow, proliferation of internal and external protocols, along with aggressive power requirements are driving an explosion in the number of asynchronous clocks in today’s SoCs.
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